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Description: Embeded-SCM Develop
ARM-PowerPC-ColdFire-MIPS
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Size: 4175872 |
Author: otman |
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Description: 基于DSP与FPGA的实时数字信号处理系统设计-Real-time digital signal processing system based on DSP and FPGA design
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Size: 32768 |
Author: Lee |
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Description: 中断闪灯（CPLD）文件夹中为FPGA部分程序，中断闪灯（DSP）文件夹中为DSP部分程序。中断闪灯（CPLD）中主要是提供DSP工作中所需要的相关信号。在中断闪灯（DSP）中主要实现外部的开关按钮S1的触发产生中断，DSP接收到相关中断信号后，跳转到闪灯子程序中，指示灯HL4开始闪烁。-Interrupt flash (CPLD) folder for FPGA part of the program to interrupt flash (DSP) folder for the DSP part of the program. Interrupt the flash (CPLD), mainly related signal in DSP. Interrupt flash (DSP) main external switch button S1 trigger an interrupt is generated the DSP receiver to the relevant interrupt signal after the jump to the flash subroutine indicator HL4 starts flashing.
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Size: 257024 |
Author: LL |
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Description: vhdl-fpga-c++-c-wireless networks-linux-verilog-cpld-arm-dsp
Platform: |
Size: 119808 |
Author: Saeid Marandi |
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Description: verilog写的回波抵消程序，相当于写了个回波抵消的芯片，不是dsp，可编译后下载于FPGA,绝对原创，写了很长时间。-Verilog echo canceller written procedures, wrote the equivalent of echo canceller chip, not dsp, can be downloaded from the compiled FPGA, absolute originality, writing for a long time.
-Verilog echo canceller written procedures, wrote the equivalent of echo canceller chip, not dsp, can be downloaded from the compiled FPGA, absolute originality, writing for a long time.
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Size: 4096 |
Author: gsder |
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Description: 联华众科FPGA开发板FA161核心器件为 Altera Cyclone系列FPGA EP1C6，FA161板载有SDRAM，SRAM，FLASH方便制作各种应用，开发板所带资料中包括了上位机与开发板USB通信，上位机与开发板以太网通信，上位机与开发板串口通信例程。FA161板载有USB 1.1，USB 2.0(CY7C68013A)接口，以太网接口(RTL8019AS)。FA161上可以进行HDL程序开发，可以进行nios ii程序开发，可以结合MATLAB制作DSP Builder应用。FA161上可以运行uClinux和Micro C/OS-II实时操作系统。-Lianhua Branch FPGA development board FA161 core device for Altera Cyclone series FPGA EP1C6 FA161 onboard SDRAM, SRAM, FLASH facilitate the production of a variety of applications, including the host computer and the development board development board brought information USB communication, the PCdevelopment board Ethernet communication, the host computer and the development board serial communication routines. The FA161-board have USB 1.1, USB 2.0 (CY7C68013A) interface, Ethernet interface (RTL8019AS). HDL program development, FA161 can be nios ii program development, combination of MATLAB production DSP Builder application. The FA161 can run uClinux and Micro C/OS-II real-time operating system.
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Size: 2085888 |
Author: qchwu |
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Description: FPGA对C6000DSP的EMIF配置，适合FPGA和DSP双核系统设计参考-Design EMIF of C6000 by Verilog HDL
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Size: 286720 |
Author: 惠言 |
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Description: dsp与fpga通信的verilog程序，强烈推荐欢迎参考-dsp and fpga verilog communication program, it is strongly recommended to welcome reference
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Size: 2048 |
Author: |
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Description: dsp 与fpga通通过中断交换数据的dsp程序C语言编写，非常完整，编译通过下载即用-dsp and fpga through exchanging data via interrupt dsp procedures C language, very complete, the compiler that is used by downloading
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Size: 275456 |
Author: |
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Description: DSP的McBsp接口的实现，不过是作为DSP的从机-The realization of McBsp interface of DSP,But the Base is the FPGA as a slaver.
Platform: |
Size: 114688 |
Author: linxin |
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Description: BF537开发板上用fpga实现AD采样，DSP用DMA将fpga内的数据读回dsp-BF537 development board with fpga implementation AD sampling, DSP DMA will use the data read back fpga dsp
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Size: 6144 |
Author: 张鑫 |
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Description: 联合FPGA和DSP的工程文件，可联合调用，实现电压信号的采集处理，并显示在液晶屏上-Joint FPGA and DSP engineering documents, can be combined call to achieve voltage signal acquisition and processing, and display on the LCD screen
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Size: 3168256 |
Author: niczeger |
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Description: FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信-FPGA SPI Timing interpretation covering all main modules communicate with the DSP
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Size: 430080 |
Author: yangtaoli |
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Description: 使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas
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Size: 492544 |
Author: 夏小保 |
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Description: 传号反转码CMI的实现，包含FPGA和DSP两部分的完整工程-CMI Code Mark Inversion of implementation, including FPGA and DSP two parts of the complete works
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Size: 153600 |
Author: bsyy |
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Description: 航空板上TMS320C6701 DSP配置EMIF，读写SDRAM FLASH 和FPGA等外围电路的源码-Aviation board TMS320C6701 DSP configuration EMIF, literacy SDRAM FLASH and FPGA source code and other peripheral circuits
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Size: 313344 |
Author: liupeng |
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Description: 用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.
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Size: 1441792 |
Author: 董明岩 |
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Description: 实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d-Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d
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Size: 665600 |
Author: 董明岩 |
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Description: Altera Stratix II FPGA与TS201 DSP通过链路口通信的程序-Altera Stratix II FPGA and TS201 DSP through a chain junction communication procedures
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Size: 6531072 |
Author: 路永轲 |
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Description: DSP TS201总线通信程序，与Altera Stratix II FPGA-DSP TS201 bus communication procedures, and the Altera Stratix II FPGA
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Size: 15360 |
Author: 路永轲 |
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